The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing an MOS type transistor.
Recently, an MOS type transistor using a p-pocket structure to prevent the microdevice punch-through effect without increasing the impurity concentration in a channel region has been proposed. A method of manufacturing an MOS transistor having such a structure will be explained below with reference to FIGS. 1A and 1B.
Element isolation region 2 is formed on the surface of p-type semiconductor substrate 1. Gate electrode 4, of polycrystalline silicon, is then formed on substrate 1 through gate oxide film 3. shallow n.sup.- -type regions 5a and 5b are formed by ion-implanting arsenic in substrate 1, using gate electrode 4 as a mask. Boron is then ion-implanted in substrate 1 at an acceleration voltage of 80 kV and a dose of 3.times.10.sup.12 /cm.sup.2 to form p.sup.+ -type regions 6a and 6b (FIG. 1A).
CVD-SiO.sub.2 layer 7 is deposited over the entire surface of the resultant structure. Layer 7 is then removed using reactive ion etching (RIE) so that it remains on only the side walls of gate electrode 4 and gate oxide film 3. N.sup.+ -type regions 8a and 8b are then formed by ion-implanting phosphorus in substrate 1, using remaining SiO.sub.2 layer 7 and gate electrode 4 as masks. Source region 9 consists of regions 5a and 8a, and drain region 10 consists of regions 5b and 8b. P.sup.+ -type regions, so-called p-pocket regions 11a and 11b, are then formed beneath regions 5a and 5b. Protective film 12 is formed over the entire resultant structure. Contact holes 13 are then formed by selectively removing portions of protective film 12 corresponding to regions 8a and 8b. Finally, Al electrodes 14 are formed in contact holes 13, thus forming an MOS transistor having an LDD (lightly-doped drain) structure (FIG. 1B).
With the conventional manufacturing method described above, however, when ion implantation is performed using gate electrode 4 as a mask, ions not only reach the prospective formation areas for the source and drain regions, but also penetrate through gate electrode 4 and gate insulating film 3 into the underlying substrate. This results in the so-called channeling phenomenon, which causes the problem of variations in the threshold voltage of the transistor. When a p-pocket region is formed by ion-implanting, at a high acceleration voltage, boron which has a small atomic radius, the channeling phenomenon is particularly notable.
It is possible to prevent this ion penetration by increasing the film thickness of gate electrode 4. In this case, however, taking into account the formation of uniformly patterned gate electrode 4 and element evenness, it is not possible to increase the thickness of electrode 4 beyond a certain limit, the ceiling of which is 4,000 to 6,000 .ANG.. As a result, variations in threshold voltage cannot be eliminated.